1. Technical Field
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a MOS transistor having a fully silicided gate.
2. Discussion of the Related Art
Semiconductor devices widely employ discrete devices such as MOS transistors as switching devices. With the increase in the integration of the MOS transistor, the MOS transistor has been scaled down in size. As a result, the length of the channel in the MOS transistor is reduced, thereby causing a short channel effect.
To reduce the effects of the short channel effect, it is required that the junction depth of the source/drain regions in the MOS transistor be reduced. However, the reduction of the junction depth of the source/drain regions causes an increase in the area resistance of the source/drain regions. Thus, the device fails to provide a drive current sufficient to drive a high performance transistor. Therefore, a self-aligned silicide process has been proposed to reduce the area resistance of a gate electrode as well as reduce the area resistance of the source/drain regions.
The self-aligned silicide process is widely used to form a silicide layer on the source/drain regions and the gate region concurrently. In general, the thickness of the silicide layer formed on the source/drain regions must be smaller than the junction depth.
Also, with the scale-down of the MOS transistor, the thickness of a gate insulating layer has been significantly reduced to prevent the short channel effect and improve the drive current capability. The thickness reduction of the gate insulating layer increases a capacitance of the gate insulating layer and improves a drive current capability.
However, when the thickness of the gate insulating layer is reduced, polysilicon depletion may occur in the MOS transistor that uses a polysilicon layer as a gate electrode. A polysilicon depletion layer increases an electrical equivalent thickness of a gate insulating layer, and reduces drive current.
Therefore, use of a metal gate is widely studied in order to solve the polysilicon depletion. However, the metal gate has a drawback in that controlling a threshold voltage Vth of a transistor becomes difficult with a metal gate. Specifically, respective threshold voltages of an N-MOS transistor and a P-MOS transistor must be controlled to use a metal gate in a CMOS transistor. The use of different metal gates in the respective MOS transistors make fabrication processes complicated and, therefore, difficult to employ.
A method of solving the problems of the polysilicon depletion and the metal gate has been disclosed in the report entitled “Totally Silicided (CoSi2) Polysilicon; a novel approach to very low-resistive gate without metal CMP nor etching”; IEDM 2001, p. 825˜828, December of 2001, by Tavel, et. al.
However, the method proposed by this report has drawbacks in that a threshold voltage Vth is increased due to a reduction of the absolute value of a flat band voltage Vfb because a midgap material is used for a metal gate.
In order to form a silicide layer of source/drain regions and a gate silicide layer using a fully silicided gate process, it is necessary to reduce the gate height. However, if the gate height is reduced, ions are implanted into a channel region during an ion implantation process for the source/drain regions, so that leakage current of the MOS transistor may increase.